IBM & Samsung Reveal Semiconductor Design Breakthrough

IBM and Samsung Electronics have jointly announced a breakthrough in semiconductor design using a new vertical transistor architecture that has the potential to reduce energy usage by 85 per cent compared to a scaled fin field-effect transistor (finFET)¹.

The innovative design was developed at the Albany Nanotech Complex in New York, which is home to a budding ecosystem of semiconductor research and prototyping. It’s hoped that the new vertical transistor breakthrough could help the semiconductor industry continue to improve in many areas, including boosting the battery life of phones, reducing the energy usage of intensive processes and expanding IoT and edge device use cases.

“Today’s technology announcement is about challenging convention and rethinking how we continue to advance society and deliver new innovations that improve life, business and reduce our environmental impact”, Dr Mukesh Khare, Vice President, Hybrid Cloud and Systems, IBM Research. “Given the constraints the industry is currently facing along multiple fronts, IBM and Samsung are demonstrating our commitment to joint innovation in semiconductor design and a shared pursuit of what we call ‘hard tech'”.

Moore’s Law, the principle that the number of transistors incorporated in a densely populated IC chip will approximately double every two years, is quickly nearing maximum capacity. In place of using transistors that are built to lie flat upon the surface of a semiconductor, with the electric current flowing laterally, the new Vertical Transport Field Effect Transistors (VTFET) are built perpendicular to the surface of the chip with a vertical current flow.

IBM and Samsung believe the VTFET process addresses many barriers to performance and limitations to extend Moore’s Law as chip designers attempt to pack more transistors into a fixed space. The new design also influences the contact points for the transistors, allowing for greater current flow with less wasted energy. Overall, the new design aims to deliver a two times improvement in performance or an 85 per cent reduction in energy use as compared to scaled finFET alternatives¹.

IBM recently announced the 2 nm chip technology breakthrough which will allow a chip to fit up to 50 billion transistors in a space the size of a fingernail. VTFET innovation focuses on a whole new dimension, which offers a pathway to the continuation of Moore’s Law. The companies also announced that Samsung will manufacture IBM’s chips at the 5 nm node. These chips are anticipated to be used in IBM’s own server platforms.

You can find more information about the semiconductor design breakthrough from IBM & Samsung on the companies’ respective websites.

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¹ VTFET nanosheet and scaled FinFET device simulation results are compared at the same footprint and at an aggressive sub-45nm gate pitch. VTFET nanosheets provides ~ 2X performance of the scaled FinFET at equivalent power due to VTFET maintaining good electrostatics and parasitics while FinFET performance is impacted by severe scaling constraints. Or VTFET could provide as much as 85% power reduction compared to the scaled FinFET architecture as compared at an equivalent frequency on the extrapolated power-performance curves.